I have awoken from a long migraine induced sleep, but have made headway solving what is 'hopefully' my last problem with this project!
Got the display fixed to unveil the error 'White Yellow Row 4 Short'
I have been following the System 11B Repair Manual and have completed the following steps:
My inexperienced brain can't make sense of these steps or I'm getting dyslexic about how '/' works. Anyone explain the following steps to me like I'm an idiot? I can follow straight forward steps but there comes a point where compound sentences and 1/2 leave so much ambiguity I start lighting matches. I can already tell I'm not going to manage the next step either. Can someone shed some light on the meaning of 'high' and 'low'?
Got the display fixed to unveil the error 'White Yellow Row 4 Short'
I have been following the System 11B Repair Manual and have completed the following steps:
- Disconnected 1J8 and 1J10 during a switch edge test, error persists (isolated to MPU).
- Jumper tested all columns, fine.
- Jumper tested all rows, pin 4 of 1J10 fails to close.
- Skipped logic probe step (don't have one, can buy one if needed).
- Checked 560ohm resistors at SR10, all return 560ish.
Then check SR10/SR11 between the 1J10 connector pin and the *second* SR10/SR11 pin listed below - 1k ohms should be seen. Then check continuity from the second SR10/SR11 pin to the U30/U39 chips.
● 1J10 pin 1, to SR11 pin 2, to SR10 pin 1/2, to U39 pin 12 (switch row 8). U39 NAND gates pins 12,13 (high) and outputs pin 11 (low) to PIA.
● 1J10 pin 2, to SR11 pin 3, to SR10 pin 3/4, to U39 pin 8 (switch row 8). U39 NAND gates pins 8,9 (high) and outputs pin 10 (low) to PIA.
● 1J10 pin 3, to SR11 pin 5, to SR10 pin 5/6, to U39 pin 2 (switch row 6). U39 NAND gates pins 2,1 (high) and outputs pin 3 (low).
● 1J10 pin 4: KEY
● 1J10 pin 5, to SR11 pin 6, to SR10 pin 7/8, to U39 pin 5 (switch row 5). U39 NAND gates pins 6,5 (high) and outputs pin 4 (low) to PIA.
● 1J10 pin 6, to SR11 pin 7, to SR9 pin 2/1, to U30 pin 13 (switch row 4). U40 NAND gates pins 12,13 (high) and outputs pin 11 (low) to PIA.
● 1J10 pin 7, to SR11 pin 8, to SR9 pin 4/3, to U30 pin 9 (switch row 3). U40 NAND gates pins 8,9 (high) and outputs pin 10 (low) to PIA.
● 1J10 pin 8, to SR11 pin 9, to SR9 pin 6/5, to U30 pin 2 (switch row 2). U40 NAND gates pins 2,1 (high) and outputs pin 3 (low) to PIA.
● 1J10 pin 9, to SR11 pin 10, to SR9 pin 8/7, to U30 pin 6 (switch row 1). U40 NAND gates pins 6,5 (high) and outputs pin 4 (low) to PIA.
My inexperienced brain can't make sense of these steps or I'm getting dyslexic about how '/' works. Anyone explain the following steps to me like I'm an idiot? I can follow straight forward steps but there comes a point where compound sentences and 1/2 leave so much ambiguity I start lighting matches. I can already tell I'm not going to manage the next step either. Can someone shed some light on the meaning of 'high' and 'low'?
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