What's new
Pinball info

Register a free account today to become a member! Once signed in, you'll be able to participate on this site by adding your own topics and posts, as well as connect with other members through your own private inbox!

Bally memory addressing

arcadian

Registered
Joined
Jul 23, 2023
Messages
7
Location
England (the original and best)
I decided that it was time for me to get around to writing a memory map for a Bally -17 MPU board, wired for 9316A ROMs, as supplied from the factory (with E1-E2, E3-E4, E6-E7). However what I found leaves me somewhat confused. The standard configuration for a -17 MPU connects addresses A0 to A10 to the U2 and U6 ROM sockets. That's the correct number of address lines to access 2kB, the size of a 9316A standard ROM. In addition, A11 and A12 are used to select the ROM (A12 hi = ROM area, A11 hi selects U2, A11 lo selects U6). All good so far.
Note that A9 is one of those address lines, and goes to pin 22 on each of these sockets, as expected.
However, the /CS chip select on pin 21 of each of these locations is fed with /A9 (the A9 signal, but inverted). This means that the ROM will only be enabled when A9 is high. Thus the address lines to the ROMs can cover the whole 2kB, but as each ROM will only be enabled when A9 is high, we can actually only address 1kB in each device.
This seems crazy - so logically, I must have missed something. Can anyone point out the error in my logic? I hope so!
Thank you in advance,
Mark
 
/CS is pin 20 so your address lines A0-A10 should be as you expect and with pin 21 as A9.

The circuit diagram has some funky labels on the 2716 ROM chips, but if you look at a pinout from the manufacturer you'll see.

Hth

Tim
 
Thank you, Tim. I don't think it quite explains it, though.
The 9316 had three chip-select lines, which General Instrument called: CS1 (pin 20), CS2 (pin 18) and CS3 (pin 21). The purchaser could decide which of these needed to be hi, and which low, so that up to eight 9316 could be addressed without any external address decoding circuitry. This is shown on the third page of the GI 9316 datasheet. They expected A11 to A13 to be used for this purpose.
As far as I understand it, Bally decided to use CS1=lo, CS2=hi, CS3=lo to enable their ROMs.
On the -17 boards with standard (Power Play) configuration, ROM U2 is wired: CS1=A11, CS2=VUA-02-A12, CS3=/A9, whilst the "regular" A9 goes to pin 22 (which the datasheet shows as A9).
So it's that CS3 line that confuses me. If Bally set it to "ignored" then the circuit would make sense, but there is no indication on the datasheet that "ignored" was an option.

Mark
arcadeexperts.com
 
Doesn't A11-13 become an extension to the address lines such that from the CPU perspective it's direct addressing the entire ROM without worrying about paging. Looks like one big 8kb (or whatever) but in reality the ROM is made up of several discrete ICs.

So it wouldn't make sense for Bally to have the same configuration on all ICs otherwise they'd all be selected at the same time.

If the diagram doesn't show that then it might be that the drawing is wrong. Wouldn't be the first time.
 
It sounds as if you know much more about this than I do, but would the schematic for the (afaik) identical Stern Mpu-100 board provide another viewpoint, i.e. maybe show an error in the Bally paperwork? Stern did make large copies that folded out to 4x size. The early board was sometimes referred to as the '4K' board, the -35 being the '8K'.
 
I looked at a Stern diagram to verify that the Bally one is correct. As you suggest, it's much more readable than the Bally original.
The difference between U2 and U6 is that U2 takes A11 on pin 20, whereas U6 takes /A11 on pin 20. Thus it is pin 20 that selects which ROM should be enabled. This allows both ROMs to have the same set of chip selects - and therefore enables a single 9316-2516 converter to be used to read any Bally 9316 in a standard EPROM programmer.
However, my issue is that we have /A9 feeding a chip select on pin 21 of each of these ROMs, in addition to A9 feeding a normal address line on each of these chips, at pin 22. This dualling-up on A9 means that only half of each ROM is accessible to the CPU. That's what I'm looking for comments on!

However, thank you each for your thoughts thus far.

Mark
 
Back
Top Bottom